In recent years, the difference between post-silicon path delay (measured value) and pre-silicon path delay (estimated value) on a chip has become large due to microprocessing. Causes of the difference in path delays include a systematic error that is not chip-dependent (e.g., error in delay estimation at a cell library) and an irregular error unique to each chip (e.g., delay fault).
Various conventional methods for identifying an error-causing element have been provided for application to a case where a chip does not operate at a target frequency of the chip because of an irregular error unique each chip. Among such methods is, for example, a method of generating various test patterns, providing the generated test patterns to a chip, and retrieving an element causing an irregular error. Such methods are recited in Japanese Patent Laid-Open Publication Nos. 2005-257654 and 2007-108863, and taught by Bastani, Pouria, et al, “Statistical Diagnosis of Unmodeled Systematic Timing Effects”, DAC 2008, pp. 355-360.
According to the above conventional methods, however, various test patterns are made and given to a chip, and path delay is measured several times to retrieve an error-causing element, arising in a problem that the time and effort expended to identify an error (delay fault) increases and consequently invites a longer design period.